RUSSELL F. GIBBONS

OBJECTIVE

Electronic Design Engineer, Project leader / Manager

SUMMARY

Engineer/Manager with MSEE and 22 years experience in digital and analog hardware. Designed for computer, communication and test systems. Serviced medical electronic instruments. Experience in programming, product development and manufacturing. Practical, responsible problem solver with effective communication skills. Work well with all types of people.

EXPERIENCE

Marvell Semiconductor, Data Communication; Sunnyvale, CA

7/2001 - present

Design Engineering Manager, Project Manager
My team develops 10 Giga bit Ethernet PHYs, and PCI-Express chips. I manage digital design engineers; schedules, design reviews; also did hands on work with Synthesis & timing (.13micron), did initial place and route, assist with lab validation & debug; Work closely with analog team, and with backend P&R and Layout engineers. Have overall responsibility for the 10 Gig mixed signal data comm chips.

One year as Project Manager over 7 chips; work with marketing, customers, Fab & assembly house, ATE test, validation groups, qualification, and help develop internal procedures; have overall responsibility for 10 Gig product development.

Maxtor, digital storage; Milpitas, CA

6/95 - 6/2001

ASIC Design Engineer, Project lead
Project lead for 7 disk drive controller ASICs; working closely with silicon vendors, inside teams and outside consultants; set schedules, propose architecture requirements and specifications.

Worked on 3 additional digital ASICs, from start to mass-production, as a hands-on design & test engineer. My main contributions were in motor servo tracking, and buffer arbitration with host interface and embedded processor. Used Verilog HDL for logic, simulation and test vectors. Synopsys to synthesize for NEC, Lucent, and TI, standard cell and gate arrays, 0.5 through 0.13 micron libraries. Helped debug circuit boards and firmware to bring-up ASICs. Led investigations in thermo analysis and low power design.

Semaphore Communications; Santa Clara, CA

8/93 - 6/95

Sr. Hardware Design Engineer, Project leader
Designed Control logic using VHDL with Xilinx FPGA, for Ethernet LAN and Frame-relay WAN. PCBs included RISC and DSP processors, communication controllers, encryption ASIC, and memory arbitration. Brought hardware to production level. Wrote self-test code and device drivers for the boards in C, using UNIX based real-time embedded development tools. Wrote Software specifications. Hired and lead S/W engineers for my project.

Acuson, medical imaging; Mountain View, CA

10/92 - 6/93

Sr. Electrical Engineer
Designed automated test system for manufacturing. Independently developed process to save the company $250,000 a year in production cost.

I.P.T.; Palo Alto, CA

4/89 - 10/92

Digital Design Engineer
Designed small computer systems, all phases from conception to manufacturable boards: circuit design, programmable logic for state machines, schematic entry, test and debug. Wrote initialization and diagnostic programs in C and assembly language. Laid out dense high speed circuit board. Wrote manuals, proposals, and made presentations. Used PC based CAD tools. Managed several projects, with H/W & S/W engineers and technicians reporting to me. Satisfied customers with high quality. Kept projects profitable and delivered on schedule.

El Camino Hospital; Mountain View, CA

1/81 - 4/89

Biomedical Engineer
Responsible for component level repair, calibration and training on computers and medical electronics equipment. Digital and analog devices: diagnostic, monitoring, imaging, and communication systems with many peripherals. Enjoyed challenging jobs others had trouble doing. Earned the confidence of the departments I supported. Took over outside contracts: improved service and response while reducing costs.

Machine Intelligence; Palo Alto, CA

12/79 - 1/81

Electronic Tech.
Assembled, tested and repaired robotic vision system. (Half time while in college).

EDUCATION

MSEE. in Digital Electronics, San Jose State University, CA, 1992.
Electives in computer architecture, programming and math. GPA = 3.75.

B.S. in biology, minor in Physics, University of California, Santa Cruz. 1980.
Graduated in top 5%. Designed experiments as part-time Physics Lab instructor.

Electronic medical instrumentation, Foothill College, CA.
Nine courses. Top student in program.

President of school's speech and debate team

Served on Board of Directors for a non-profit organization.

Return to my web page: "Cultures of the Andes"

Last updated Mar 15, 2004